AERIS-10 is an alpha radar design, not a kit
The repository lays out a radar architecture at 10.5 GHz: frequency synthesis, data conversion, beam steering, RF front ends, an Artix-7 FPGA, an STM32 controller, antennas, power management, mechanics, and a Python display. The FPGA path includes chirp generation, baseband conversion, filtering, pulse compression, Doppler work, MTI, and CFAR detection. This is unusually broad source material for researchers, but breadth does not mean the hardware has reached kit-level repeatability.
The README labels AERIS-10 alpha and marks features as work in progress. It presents a Nexus design with an 8 by 16 patch array and a longer-range design with a 32 by 16 slotted-waveguide array. The published 3 km and 20 km figures are design specifications, not results from our lab. We did not assemble or range-test either version, and physical bring-up remains an active subject.
Issue 186 blocks a confident fabrication order
An August 23 issue asks four questions before ordering the full board set. The reporter found Gerbers, schematics, and BOMs uploaded on different dates and asks whether known board fixes are present. The same issue requests confirmation that the schematic and Gerber set match, asks for the 10-layer main-board stack-up, and notes an earlier release package that reportedly contained stale files from another project.
The main-board BOM names an XC7A50T device, while another constraint file and prior discussion refer to an XC7A200T in an incompatible package. Issue 186 asks which one represents production hardware. Its response confirms the 50T as the current target, but other synchronization questions still need answers against the exact revision sent to a fabricator. At X-band prices, a wrong footprint or layer definition is not a minor documentation flaw.
What happened when we ran it
Our sandbox installed 34 Python packages in 13 seconds and used 36 MB on disk. Building commit 749bd0f succeeded in 4 seconds. Pip-audit reported 0 known vulnerabilities in that environment. The unprivileged Debian container had 3 CPUs and 8 GB of RAM, while the checkout held 894 files, about 71,029 source lines, and occupied 225.7 MB.
There was no test script or target, so we skipped tests. Our scan found 1 CI workflow file, no Dockerfile, and no tests directory. The 4-second build did not invoke Vivado, compile STM32 firmware, run FPGA simulation, inspect PCB design rules, or start the active GUI against real radar data. It only establishes that the detected software build path completed at commit 749bd0f.
We did not measure transmit power, receiver noise, beam shape, angular accuracy, range, Doppler performance, thermal behavior, electromagnetic compatibility, or target detection. The 3 km and 20 km values remain project specifications. Teams considering this design need their own simulations, bench tests, calibrated RF equipment, controlled transmit authorization, and a staged bring-up plan.
Sixteen 10 W channels demand a multidisciplinary lab
The documented prerequisites name radar fundamentals, PCB assembly experience, Python 3.8 or newer, and Vivado for signal-processing changes. In practice, the design crosses microwave layout, phased-array antennas, power sequencing, mixed-signal conversion, FPGA timing, embedded firmware, mechanics, cooling, and visualization. The extended variant lists 16 amplifier boards using 10 W GaN devices, which raises the cost and consequence of an RF mistake.
Issue 147 asks an antenna specialist to recheck the slotted-waveguide radiation pattern, S11, input impedance, and full-array steering through simulation. Issue 175 questions capacitor selections and footprints in the RF path and proposes a substitution for one location. These are useful engineering discussions and direct evidence that builders should review the current design instead of treating downloaded manufacturing outputs as certified.
The April FPGA audit is not board bring-up
Release v2.0.2-p0-audit, published April 20, 2026, documents timing closure for an XC7A50T production bitstream. It reports all user timing constraints met and 0 failing setup, hold, or pulse-width endpoints in that Vivado run. The release also changes 400 MHz paths and removes a redundant microcontroller transmit-and-receive route because the FPGA chirp controller owns per-chirp switching.
That is useful evidence about a named FPGA build at commit ca8c586, not a verified radar. Issue 150, opened in May and active through August, discusses receiving boards and parts, assembling in Morocco, and recruiting FPGA and mechanical help for tests. The gap between timing closure and working hardware is normal, but buyers should keep those milestones separate.
Hardware and software use different licenses
Hardware documentation, including schematics, layouts, manufacturing outputs, and mechanical drawings, is under CERN-OHL-P v2. Software and firmware are under MIT terms. The README says modified hardware designs must retain notices and be distributed in source form under the same license. A company building or selling a derivative should review both license paths and track which files belong to each.
GitHub showed 24,853 stars, 13 combined issues and pull requests, and a last push on June 17, 2026. Issue and pull-request activity continued through August 24, including fabrication questions and FPGA test corrections. That is meaningful community attention after the last push, although it does not turn an alpha design into a finished instrument.
Freeze one revision before spending on fabrication
AERIS-10 offers a rare view across a phased-array radar, from RF boards to CFAR output and a map display. Researchers can study subsystem choices, reuse simulations, review firmware, or contribute corrections without building the full system. The 17-second software setup makes that desk review easy. It says nothing about fabrication readiness.
A sensible build path starts by freezing a revision and reconciling schematic, layout, BOM, and Gerbers. Answer the FPGA and stack-up questions, simulate the antenna, then bring up power and digital sections before any RF transmission. Teams without that process should start with existing SDR or mmWave hardware. PLFM_RADAR is valuable open engineering work in progress, not a proven radar kit.