mrkeyoor.com_
Thu 29 Oct 13:14 UTC
AI3 min read

Qwenputer compiles a RISC-V CPU into Qwen3.5-4B

The experimental model runs calculations through compiled transformer layers. Its RISC-V version needs the RvChat driver, and the published test results come from the developer.

Divyansh Agrawal describes Qwenputer, an experimental modification of Qwen3.5-4B that executes a RISC-V CPU inside the model's forward passes, in his October 22, 2026 write-up. The project puts calculation inside the modified model, but its RISC-V version still needs a driver to manage execution. The supplied results are the developer's tests; no independent measurements accompany this article.

A compiler supplies the computer

The repository describes 11 compiled transformer layers placed before Qwen's own layers. A compiler sets the computer's weights directly, while Qwen's original weights stay unchanged. This is a constructed machine inside a modified model. It does not demonstrate that the base model learned to execute RISC-V.

Memory comes from Gated DeltaNet, the recurrent state used by Qwen's architecture. The project configures it so a write replaces one addressed row and a read retrieves that row. The CPU stores its program and working data there. Generated trace tokens record the machine's execution, according to the repository's technical description.

Qwen requests a calculation through the tool-call syntax it was trained to use. The added layers execute the calculation and emit the response. The repository says the calculation happens internally: an external Python interpreter does not execute that request. The familiar request format and the location of execution are separate details.

Internal execution still needs a driver

The RISC-V version needs RvChat to load firmware into the DeltaNet state and keep CPU trace tokens out of Qwen's language layers. Agrawal's limitations section says it doesn't run with a plain generate() call yet. Developers evaluating this version should start with the repository's RISC-V quickstart and its driver requirement.

That distinction also matters when reading the repository: its separate, earlier CHIP-8 version has a plain generate() example. That example does not establish the same compatibility for the RISC-V version discussed here.

The repository's benchmark table reports greedy decoding and 40 problems per set. On synthetic integer arithmetic, Qwenputer scores 97.5%, versus 75.0% for base Qwen3.5-4B and 97.5% for base Qwen with a host Python tool. These are developer-reported arithmetic results. This small, targeted evaluation does not establish general reasoning gains or a speed advantage over Python.

There are costs to placing the CPU here. Agrawal's write-up lists an 18.8 GB checkpoint, mostly zero padding. He also reports that a big calculation takes seconds rather than milliseconds because each CPU instruction costs a few decoded tokens. Developers exploring compiled computation inside model weights have a concrete experiment to inspect. Those who need plain generate() compatibility for this RISC-V version should account for the driver limitation before integrating it. Independent replay of execution traces and measurements of complete calculation latency would help assess it beyond the published arithmetic scores.

Sources

  1. Qwenputer: a fully functioning, deterministic RISC-V CPU inside Qwen3.5
  2. divagr18/qwenputer repository
  3. Qwen3.5-4B-Qwenputer model card